CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

Abstract

Chaos is one of the important research areas in recent years. The chaotic signal generator is oneof the most basic structure in the chaos-based researches and applications. In this study,Sundarapandian-Pehlivan Chaotic Oscillator (SPCO) designs have been implemented in 2different platforms as analog-based using Second-Generation Current Controlled CurrentConveyor (CCII) and FPGA-based with one of the chaotic oscillator that has been presented tothe literature namely Sundarapandian-Pehlivan system. The structure used for the design ofCCII-based chaotic oscillator and the results obtained from the study have been presented. In thesecond phase, the design of SPCO has been realized in order to utilize for running in FPGAchips using Dormand-Prince (DP) numeric algorithm. The design has been coded in VHDLusing 32-bit IEEE-754-1985 floating point representation. The designed system has been testedby synthesizing it in Xilinx ISE Design Tools program. Then, the test results obtained from DPbased SPCO structure have been presented. In the last phase, the designed system has beensynthesized for VIRTEX-7 FPGA. FPGA chip resource consumption values that obtained afterthe Place-Route process are presented. According to the results, the maximum operatingfrequency of DP-based SPCO unit on FPGA is obtained as 362.608 MHz. In future studies, thedesigns of Pseudo Random Number Generator (RNG) and True RNG can be performed usingDP-based SPCO unit implemented successfully in this study.