Now showing items 1-3 of 3
Fixed and Floating point-Based High-Speed Chaotic Oscillator Design with Different Numerical Algorithms on FPGA
In this paper, the design of 3D PC chaotic system has been implemented using Euler, Heun, RK4 and RK5-Butcher numerical algorithms in VHDL with 32 bit IQ-Math fixed point number format (16I-16Q) on FPGA. The chaotic ...
High speed FPGA-based chaotic oscillator design
(Microprocessors and Microsystems, Elsevier, 2019)
In this study, autonomous Lü-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math fixed-point number format for developing embedded chaosbased engineering applications. ...
Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator
In this paper, a novel chaos-ring based dual entropy core TRNG architecture on FPGA with high operating frequency and high throughput has been performed and presented. The design of dual entropy core TRNG has been generated ...