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Yapay Sinir Ağları-Tabanlı 3-B Yeni Jerk Kaotik Osilatörünün FPGA Üzerinde Tasarımı ve Gerçeklenmesi
(2018)
In this paper, the 3-D novel Jerk chaotic system has been coded in Very High Speed Integrated Circuits Hardware Description Language (VHDL) with 32-bit IEEE-754-1985 floating point number standard for real-time Artificial ...